The present invention relates generally to the computer art. More particularly, the present invention pertains to the manipulation and transfer of data in a computer system. Specifically, the present invention relates to an improvement in data bus architecture, including a means and method for latching data states on a data bus to optimize bus utilization.
Generally, a bus comprises a grouping of signals, a communication link between one or more computer components and an associated communication (usage) protocol. The rate at which data can be transferred over the bus from one component to another has a direct effect on the operating speed for the overall computer system. Accordingly, bus utilization schemes or techniques seek to optimize the percentage of bus time which can be used for data transfer.
The various components of the computer system which are connected to the data bus are generally referred to as nodes. These nodes typically are characterized as either driving nodes or receiving nodes or both and typically comprise large scale integrated circuits or chips. Those nodes that act as drivers actively drive data onto the bus by forcing each line in the bus to assume a particular data state. Those nodes that act as receivers sample data from the bus after it has bee driven to a particular state by a driver node. Communication between selected ones of the nodes in the computer system is accomplished under control of the bus protocol, which specifies the time-multipexing of data on the bus.
Baseband buses generally prohibit the driving of data onto the bus by more than one driver at a time. At least two reasons exist for this prohibition, namely, (1) simultaneously driving two or more data states onto the bus creates an indeterminate data state on the bus, which precludes the accurate transfer of any data state when the bus is then sampled by the receiving nodes, and (2) some types of drivers create electrically harmful or dangerous conditions if driven simultaneously on the same bus, such as noise, signal spikes and short circuits.
Typical systems now operate under this constraint in various ways to attempt to optimize data transfer rates and bus utilization. One well known scheme employs tri-state drivers and separate timing events to disable and enable successive driver nodes. Tri-state drivers create power transients which are harmful to the computer system at large when drivers connected to the same line simultaneously attempt to drive that line to conflicting states. Accordingly, one driver must be completely disabled before the succeeding driver is enabled. During the time period required for disabling one driver and enabling the next driver no data may be sampled from the data bus. Accordingly, this represents down time for the bus and reduces the bus utilization. This results in a reduction in data bandwidth, i.e., the amount of information transmitted per unit time, for the computer system. This shortcoming exists, even in light of significant advances in overall system timing, as the time required for driver enabling and disabling has not been reduced in proportion to the reduction in data transfer times afforded through other advances.
An alternative method for data transfer uses open terminal drivers. These open terminal devices drive the data bus lines to only a single state. The other state is provided through a static resistor which holds the data bus line in a particular state unless driven to an opposing state by a driver. Open terminal drivers may simultaneously drive a given bus line because all the active drivers are trying to drive the bus to the same state and the only opposing force is the relatively weaker resistor trying to drive the bus to the opposite state. In addition, no more current flows through the resistor when several devices are enabled than when only one driver is enabled. This method thus allows the overlap of the disable time for a first driver with the enable time for a second, succeeding driver.
However, the simple switch to the open-terminal driver configuration does not necessarily optimize bus utilization. The resistance used to pull non-driven bus lines to the opposing logic state presents a trade-off between bus power and bus speed. High impedance resistors provide for low power consumption, but restrict bus bandwidth. To obtain sufficiently high system bandwidth, these resistors must be low impedance to provide short signal transitions and readily overcome the capacitance of the bus and its nodes. However, lowering the impedance of these resistors increases the current drive required of the bus drivers and increases the power which must be dissipated by these resistors when the corresponding bus line is driven.
Accordingly, current techniques for data bus transfer control provide an undesirable or unattractive trade-off between system power requirements and data bus utilization. Tri-state drivers provide low power data transfer, but require unsatisfactory driver hand-off time (the time required for one driver to disable and another driver to enable for data transfer); open terminal drivers allow the enable and disable times for successive drivers to overlap, thus reducing inefficient hand-off time and increasing bus utilization, but increase the power requirements for the system--an increase which can represent unacceptable operating performance.